Enum CodeGenTarget
Code gen target to register/initialize
public enum CodeGenTarget
Fields
AArch64 = 2
ARM AArch64 target
AMDGPU = 3
AMD GPU target
ARM = 4
ARM 32 bit targets
All = 2147483647
All available targets
BPF = 6
Berkeley Packet Filter (BPF) target
Hexagon = 7
QUALCOMM Hexagon DSP/NPU family
Lanai = 8
Un[der]documented Google (Myricom) processor
MIPS = 10
MIPS target
MSP430 = 11
TI MSP430 Mixed-signal micro-controller
NVPTX = 12
Nvidia Parallel Thread Execution (Nvidia GPUs)
Native = 1
Native target of the host system, generally used for JIT execution
None = 0
Default invalid target; No/None is never a valid target
PowerPC = 13
PowerPC target
RISCV = 14
RISC-V target
SPIRV = 16
Standard Portable Intermediate Representation [Generic GPU][Vulcan and later DirectX]
Sparc = 15
Sparc target
SystemZ = 17
z/Architecture (IBM 64 bit CISC)
VE = 18
NEC's Vector Engine
WebAssembly = 19
WebAssembly target
X86 = 20
X86 target
XCore = 21
XMOS core