Enum CodeGenTarget
Code gen target to register/initialize
public enum CodeGenTarget
Fields
AArch64 = 2ARM AArch64 target
AMDGPU = 3AMD GPU target
ARM = 4ARM 32 bit targets
All = 2147483647All available targets
BPF = 6Berkeley Packet Filter (BPF) target
Hexagon = 7QUALCOMM Hexagon DSP/NPU family
Lanai = 8Un[der]documented Google (Myricom) processor
MIPS = 10MIPS target
MSP430 = 11TI MSP430 Mixed-signal micro-controller
NVPTX = 12Nvidia Parallel Thread Execution (Nvidia GPUs)
Native = 1Native target of the host system, generally used for JIT execution
None = 0Default invalid target; No/None is never a valid target
PowerPC = 13PowerPC target
RISCV = 14RISC-V target
SPIRV = 16Standard Portable Intermediate Representation [Generic GPU][Vulcan and later DirectX]
Sparc = 15Sparc target
SystemZ = 17z/Architecture (IBM 64 bit CISC)
VE = 18NEC's Vector Engine
WebAssembly = 19WebAssembly target
X86 = 20X86 target
XCore = 21XMOS core